A Successful DFT Tester: What Will It Look Like? Is Revolution in Test Approaches Required?

For many years, the semiconductor industry has been predicting the emergence of DFT tester market, enabled by increasing number of devices being designed with DFT methodologies such as scan and BIST. The search for low cost DFT tester solutions has resulted in the first ITRS roadmap for a DFT tester in 1999 and a major revision of this roadmap in 2001. While it is generally understood that a DFT tester can be used to limit the digital test performance envelope in production testing, some trends in the industry, such as increase in mixed signal SOC designs and multi GHz serial IO interfaces, may be pushing the industry toward more highly configurable and higher performance test solutions. The relative immaturity of analog mixed signal DFT, coupled with increasing proliferation of mixed signal SOC devices, may also prevent the wholesale industry-wide adoption of digital-only DFT testers. In addition, the emergence of novel fault models, beyond the traditional SSA model, to cover the emerging defects found in advanced silicon technologies have been noticeably lacking. Adding to the fire has been continuing discussion of the now famous $200/pin tester, which highlights the pressure faced by ATE companies in looking for a viable business model that can provide both high performance and low cost DFT testers at the same time. The result of this cloudiness in the industry has been relative slowness in the development of DFT testers by the ATE industry. However, the fact that adoption of DFT in devices is continuing leads us to believe that a DFT tester market will emerge eventually. The question is what kinds of DFT testers can best exploit the opportunities presented in this cloudy market. This is the first of two sessions that will explore various approaches in DFT tester development, features that may determine the success of DFT testers, and potential catalysts that may cause wide-scale industry adoption of DFT testers. This session explores whether successful DFT testers will take revolutionary departures from current mainstream testers. Proceedings of the 20 th IEEE VLSI Test Symposium (VTS’02) 1093-0167/02 $17.00 © 2002 IEEE